1. Field of the Invention
This invention generally relates to a frequency multiplier circuit, and especially to a rational number frequency multiplier circuit.
2. Description of the Related Art
A frequency multiplier circuit, when used in a digital system, can generate clock pulse signals of integrated circuit. In general, the frequency multiplier circuit comprises a phase lock loop (PLL). FIG. 1 is a circuit block diagram of a conventional phase lock loop, which comprises four sub-circuit systems: a phase detector (PD), a charge pump (CP), a loop filter (LF) and a voltage controlled oscillator (VCO). The phase detector PD detects a difference between a reference signal and an inner oscillating signal, and transforms the compared result to two digital signal output. The charge pump CP transforms the two digital signals to a control voltage output. The loop filter LF filters high frequency portion of the control voltage. The voltage controlled oscillator VCO transforms the control voltage to an oscillating frequency output. However, when multiplying the reference frequency, the oscillation frequency of the voltage controlled oscillator VCO has to be increased and an additional frequency divider FD is needed, as shown in FIG. 2, such that the output frequency, which is a multiplication of the reference frequency, is fed back and frequency-divided, and then compared with the source reference frequency. Therefore, the signal with N multiple frequency can be obtained by simply adjusting frequency-divided number N of the frequency divider.
Another conventional technology is disclosed by Taiwan Patent No. 35662. However, the technology can only generate the integer multiple frequency. When producing a non-integer multiple frequency, a non-integer division must be performed by the frequency divider FD as shown in FIG. 2, which can be achieved by a Fractional-N frequency synthesizer which has a more complex circuit.